Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs

[[abstract]]In this paper, we propose an algorithm based on a framework of reconfigurable multiple scan chains for system-on-chip to minimize test application time. The control signal combination causes the computing time increasing exponentially, and the algorithm we proposed introduces a heuristic control signal selecting method to solve this serious problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan chains. The results show that it could significantly reduces both the test application time and the computation time.[[notice]]補正完畢[[incitationindex]]EI[[booktype]]紙

A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits

[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns can't detect fault (called useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In fact, a random test set includes many useless patterns. Therefore we present a technology, including both reseeding and bit modifying (a.k.a. pattern mapping) to remove useless patterns or change them to useful patterns. When patterns changed, we pick out number of different fewer bits, leading to very short test length. Then we use an additional bit counter to improve test length and achieve high fault coverage. The technique we present is applicable for single-stuck-at faults. Experimental results indicate that complete fault coverage-100% can be obtained with less test time.[[notice]]補正完畢[[journaltype]]國際[[incitationindex]]EI[[ispeerreviewed]]Y[[booktype]]紙本[[countrycodes]]TW

An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction

[[abstract]]Recently, power dissipation in full-scan testing has brought a great challenge for test engineers. In addition to shift power reduction, excessive switching activity during capture operation may lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response per capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time. Experimental results for ISCAS'89 benchmark circuits show that the capture power reduction in test sequence can up to 55%.[[notice]]補正完畢[[incitationindex]]EI[[booktype]]紙

Power-aware compression scheme for multiple scan-chain

[[abstract]]As test data continues to grow quickly, test cost also increases. For the sake of decreasing the test cost, this article presents a new data dependency compression scheme for large circuit which is based on multiple scan chains. We propose new compression architecture with fixed length for running tests. In results, when the complexity of a VLSI circuit is growing, the number of input pins for testing is very low. Since test data in power aware is not changed frequently, we use a selector to filter the unnecessary status and buffers to hold the back data. We also propose a new algorithm to assign multiple scan chains and an improved linear dependency compute method to find the hidden dependency between scan chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power.[[incitationindex]]SCI[[booktype]]紙本[[booktype]]電子

Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment

[[abstract]]As the test data continues to grow quickly, test cost also increased. For the sake of decreasing the test cost, this study presents a new compression for large circuit, which is based on multiple scan-chains and unknown structure. The proposed method is targeted at intellectual property cores and system-on-a-chip. The authors consider the shift-in power and compression ratio in low-cost automatic test equipment (ATE) environment. A new compression architecture with fixed length for running ones is proposed. For the proposed method, the ATE has no repeated function and synchronisation signal. In the results, when the complexity of very large-scale integrated circuit is growing up, the number of input pins for testing is very low. The average compression ratio of our method is 63% for MinTest and TetraMAX on ISCAS'89 benchmarks. The average of peak/weight transition count shift-in turns to 3x/6.6x for MinTest and 2.3x/5.6x for TetraMAX, after comparing selective scan slice and the proposed method. The average of hardware overhead is 6% for MinTest and 6.5% for TetraMAX.[[incitationindex]]SCI[[incitationindex]]EI[[booktype]]紙

An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing

[[abstract]]In recent years the advance of CMOS technology has led to a great development, especially on the complexity of the system-on-chip (SOC). As the development of circuit with different technology, the embedded cores embedded into system-on-chips (SOCs) usually have multi-frequency to drive it. In this paper, we present a heuristic approach of TAM optimization according to the reality and reduce the test application time. The proposed method is applicable to the design model with hierarchy SOCs. We pay the price in hardware overhead in order to decrease test application time.[[incitationindex]]EI[[booktype]]紙

Compact Test Pattern Selection for Small Delay Defect

[[abstract]]This letter proposes an algorithm that selects a small number of test patterns for small delay defects from a large N-detect test set. This algorithm uses static upper and lower bound analysis to quickly estimate the sensitized path length so that the central processing unit (CPU) time can be reduced. By ignoring easy faults, only a partial fault dictionary, instead of a complete fault dictionary, is built for test pattern selection. Experimental results on large International Test Conference benchmark circuits show that, with very similar quality, the selected test set is 46% smaller and the CPU time is 42% faster than that of timing-aware automated test pattern generation (ATPG). With the proposed selection algorithm, small delay defect test sets are no longer very expensive to apply.[[incitationindex]]SCI[[incitationindex]]EI[[booktype]]紙